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-- Company: 
-- Engineer:
--
-- Create Date:   14:41:09 05/19/2011
-- Design Name:   
-- Module Name:   C:/Users/Geoff/Documents/Degree/CSSE2000/Vcode/theproject/Register_Test.vhd
-- Project Name:  theproject
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: proc_registers
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.proc_package.ALL; 
ENTITY Register_Test IS
END Register_Test;
 
ARCHITECTURE behavior OF Register_Test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT proc_registers
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         en : IN  std_logic;
         p_0_wr_en : IN  std_logic;
         p_0_addr : IN  std_logic_vector(3 downto 0);
         p_0_datain : IN  std_logic_vector(7 downto 0);
         p_0_dataout : OUT  std_logic_vector(7 downto 0);
         p_1_addr : IN  std_logic_vector(3 downto 0);
         p_1_dataout : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal en : std_logic := '0';
   signal p_0_wr_en : std_logic := '0';
   signal p_0_addr : std_logic_vector(3 downto 0) := (others => '0');
   signal p_0_datain : PROC_REG_DATA_TYPE := (others => '0');
   signal p_1_addr : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal p_0_dataout : std_logic_vector(7 downto 0);
   signal p_1_dataout : std_logic_vector(7 downto 0);
	signal myout:std_logic_vector(7 downto 0);
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: proc_registers PORT MAP (
          clk => clk,
          rst => rst,
          en => en,
          p_0_wr_en => p_0_wr_en,
          p_0_addr => p_0_addr,
          p_0_datain => p_0_datain,
          p_0_dataout => p_0_dataout,
          p_1_addr => p_1_addr,
          p_1_dataout => p_1_dataout

        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
      

      wait for clk_period*50;
		--setup some registers
         
         p_0_addr <="0001";
         p_0_datain <="00010001";
			en <='1';
			p_0_wr_en <='1';
			wait for clk_period;
			p_0_addr  <="0010";
         p_0_datain <="00000001";
			wait for clk_period;
			en <='0';
			p_0_wr_en <='0';
			wait for clk_period;
		
		--Test Mov function 					
				--The address of the data souce 
				p_1_addr <= "0001";
				--The address of the recieving register
				p_0_addr <= "0011";
				--allowws the register to write the data at p_0_datatin to be 
				-- written to the p_0 Register
				p_0_wr_en <='1';
			
				en <='1';
				wait for clk_period;
				myout <=  p_1_dataout;
				wait for clk_period;
				p_0_datain <= myout;
				wait for clk_period;
				p_0_wr_en <='0';
				en	<='0';
      wait;
   end process;

END;
